CPU와 Device사이의 데이터 교환

Lecture11

//Two ways a device can send a message to the CPU
1) continuous  Polling from the CPU
2) Interrupt from the Device

장치가 CPU에 정보를 전달하는 방법은 1) CPU로부터의 지속적인 Polling, 2) 장치로부터의 Interrupt 두 가지가 있으며, 두 방법은 각기 다른 장단점을 갖고 있다.

//Interrupt configuration
1) Shared Interrupt Request Line(INTR) + One-Time polling(INTA)
2) Shared Interrupt Request Line(INTR) + Daisy Chained Interrupt Acknowledge Line(INTA)

3) INTR through Encoder INTA through Decoder + INTA through Decoder
=> If the INTA is Daisy Chained Then devices sends Interrupt Number after Receiving INTA
4) PIC(Programmable Interrupt Controller)

//Direct Memory Access(DMA)
Direct Memory Access allows a device to directly Read or Write memory without going through the CPU. This can save time if the device has much data to Read or Write

DMA는 CPU를 경유하지 않고 메모리에 읽기/쓰기를 가능하게 하며, 장치가 많은 데이터를 읽기/쓰기할 때 소요되는 시간을 절약할 수 있다. 

//A Device Writes to Memory
-> without DMA
1) Device sends INTR
2) CPU reads Data from the Device to CPU Register
3) CPU writes Data to Memory
-> With DMA
1) Device sends INTR
2) Device directly Writes to Memory

이렇게 CPU가 CPU 레지스터를 읽고 쓰는 과정이 생략되면서, 시간이 절약된다.

//A Device reads from Memory
-> without DMA
1) Device sends INTR
2) CPU reads Data from Memory to CPU register
3) CPU Write Data to Device from Register
-> with DMA
1) Device sents INTR
2) directly Reads Data from Memory
이렇게 CPU가 CPU 레지스터를 읽고 쓰는 과정이 생략되면서, 시간이 절약된다.

//Normally a block of data is sent between a device and Memory, when DMA is used
We need to know
1) Reading or Writing Memory
2) Location in Memory(Memory Address)
3) How much data?

데이터가 교류될 때 필요한 정보 세 가지는 1)R/W, 2)메모리 주소, 3)데이터의 양이다.

 

//A DMA Device(any device using DMA) has extra DMA Registers in its Controller Card

DMA 장치는 컨트롤러 카드에 추가적으로 DMA Register가 존재한다. 

- Status Register(상태 레지스터) : R/W bit(읽기인지 쓰기인지), Done bit(완료 여부)

- Start Address(메모리 주소)

- Word Count(데이터의 양)

 

//DMA Operation Steps
Example: A Camera takes a Picture
1) Device sends INTR to CPU
2) Device waits for INTA
3) CPU runs Interrupt Service Routine(ISR)
4) CPU sends Start Address, Word Count and Direction(R/W) to Device
5) CPU starts the Data Transfer
6) While the device is sending data to Memory then the CPU can do something else. If the CPU wants to use the Bus, then the CPU must share the Bus with the DMA Device
7) Device finisheds Data Transfer
8) Device sends another INTR
9) CPU sends INTA
10) CPU reads Done Bit meaning that the Transfer is complete

//There can be multiple DMA Devices sharing the bus. How to share the Bus? The method used to share the bus is called "Bus Arbitration"
버스를 효과적으로 공유하기 위해서 중재하는 방법을 BUS Arbitration이라고 한다.

 

Bus Arbitration:

The main purpose of Bus Arbitration is to choose one device to use the bus at one Time. The one device currently using the bus is called the "Bus Master". The Bus Master is the device which can currently send Read and write operations to the Bus.

Bus Arbitration의 목적은 어떤 순간에 어떤 장치가 버스를 사용하게 하는 지 선택하는 것이다. Bus를 현재 사용하고 있는 장치를 버스 마스터라고 한다.

The Bus Master can be
-CPU
-A DMA Device

버스 마스터는 CPU가 될 수도 있고, DMA 장치가 될 수도 있다.
=>
If the CPU is Bus Master then the CPU send Read and Write Operations to
- Memory
- Any Device

버스 마스터가 만약 CPU라면 CPU는 R/W 동작을 메모리 또는 장치에 전달한다.
If a DMA Device is the BUS Master then it is Reading and Writing Memory

버스 마스터가 만약 DMA장치라면 R/W 동작은 메모리에 전달할 것이다. 

Two kinds of Bus Arbitration
1) Centralized Arbitration: One device is the BUS Arbiter(버스 중재자). The Bus Arbiter chooses the Bus Master.
- The CPU can be the Bus Arbiter
- The Bus itself can be the BUS Arbiter
- A separate device might be the Bus Arbiter

CPU, 버스, 장치 중 하나가 버스 중재자가 되며, 이 버스 중재자가 버스 마스터를 선택한다. 
2) Distributed Arbitration: All device work together to choose a Bus Master. There is no Bus Arbiter.

모든 장치들이 협력하여 버스 마스터를 선택한다. 따라서 버스 중재자가 따로 없다. 

 

Lecture12

Bus Arbitration
Centralized Arbitration: One Device is the Bus Arbiter

하나의 장치가 버스 중재자가 되는 방법.

 

The Bus Arbiter can be
- The CPU
- The Bus itself
- A separate device called the 'DMA Controller'

 

The purpose of the Bus Arbiter is to choose the Bus Master

There needs to be some extra lines in the bus:
- Bus Request(BR): activated by a device which wants to become the Bus Master
- Bus Grant(BG): sent from the Arbiter to the device which will become the next Bus Master
- Bus Busy(BBSY): Active while any device is the Bus Master

Steps to become Bus Master
1) Device Requests to become Bus Master by activating BR
2) Arbiter waits until BBSY is not active
3) Arbiter sends BG to device
4) Device receives BG and Becomes Bus Master

//While a device is Bus Master
1) Keep BBSY active
2) Transfer Data between device and Memory
3) When Data Transfer is finished:Deactivate BBSY, and set Done Bit
4) Send INTR to CPU

//How much data should be sent whild a device is Bus Master?
1) Send all Data(Burst Mode)
- Fastest Possible Data Transfer
- Long Delay for CPU
2) One Word is Sent, then device gives up Bus(Deactivating BBSY), and requests to become Bus Master again(Activating BR)(CycleStealing Mode)
-No Long Delay for CPU
-Data takes longer to send
3) Device Monitors the Bus Request Line, and Gives up the Bus after some time if another device wants to be Bus Master, The device then Requests to be Bus Master agin (Transparent Mode)
=> good complement

//Distributed Arbitration
- All DMA Devices work together to choose a Bus Master
- We need to add some lines to the Bus
- No Bus Arbiter
- No BR Line
- No BG Line
- Need BBSY and Need Arbitration Lines ARBO, ARB1, ... , ARBN

Arbitration Lines
-------------------------------------- INTR
-------------------------------------- BBSY
-------------------------------------- ARBO
-------------------------------------- ARB1
-------------------------------------- ARB2
-------------------------------------- ARB3
                     
Each Device is identified by a different Arbitration Code
When a device wants to become the Bus Master, it will send its Abitration Code to the Bus
The Active Arbitration Lines on the Bus are the Bitwise OR of all devices sending their Arbitration Codes

Both Device send their Arbitration Codes
1010 + 1101 -> 1111 <- Arbitration Lines
All DMA Devices Read Arbitration Lines
If a device is Sending '0' but Reading '1' Then that device changes all Later Bits to '0'

step  DMA1                 DMA2
1       send 1010         send 1101
2       read 1111          read 1111
3       send 1000          send 1100
4       read 1100          read 1100
5       send 1000          send 1101
6       sead 1101          read 1101
7       send 1000       
=> Device reads its own Code DMA2 Becomes Bus Master!
=> highest arbitration Code Becomes bus master